Timing Information
Figure 4–17. Read Operation Timing
nCS
t
CH
DCLK
t
t
CL
t
nCLK2D
ODIS
DATA
ASDI
Bit N
Bit N
1
Bit 0
Add_Bit 0
Table 4–13 defines the serial configuration device timing parameters for
read operation.
Table 4–13. Read Operation Parameters
Symbol
Parameter
Min
Max
Unit
fRCLK
Read clock frequency (from
FPGA or embedded processor)
for read bytes operation
20
MHz
tCH
25
25
ns
ns
ns
ns
DCLKhigh time
tCL
DCLKlow time
tODIS
tnCLK2D
Output disable time after read
Clock falling edge to data
15
15
4–26
Core Version a.b.c variable
Altera Corporation
July 2004
Configuration Handbook, Volume 2