Serial Configuration Devices (EPCS1, EPCS4, EPCS16 & EPCS64) Data Sheet
Figure 4–20. Altera Serial Configuration Device 16-Pin SOIC Package Pin-Out
Diagram
EPCS16 or
EPCS64 Device
1
2
3
16
V
V
DCLK
ASDI
N.C.
N.C.
N.C.
N.C.
GND
CC
15
CC
(1)
(1)
14
N.C.
N.C.
(1)
(1)
(1)
(1)
(1)
(1)
4
5
6
7
13
12
11
N.C.
N.C.
10
9
nCS
DATA
8
V
CC
Note to Figure 4–20:
(1) These pins can be left floating or connected to Vcc or GND, whichever is more
convenient on the board.
Table 4–20. Serial Configuration Device Pin Description
Pin Name Pin Number Pin Type
Description
2
Output
DATA
The DATAoutput signal transfers data serially out of the serial
configuration device to the FPGA during read/configuration
operation. During a read/configuration operations, the serial
configuration device is enabled by pulling nCSlow. The DATAsignal
transitions on the falling edge of DCLK.
5
1
Input
Input
The AS data input signal is used to transfer data serially into the
serial configuration device. It receives the data that should be
programmed into the serial configuration device. Data is latched in
the rising edge of DCLK.
ASDI
nCS
The active low chip select input signal toggles at the beginning and
end of a valid instruction. When this signal is high, the device is
deselected and the DATApin is tri-stated. When this signal is low, it
enables the device and puts the device in an active mode. After
power up, the serial configuration device requires a falling edge on
the nCSsignal before beginning any operation.
6
Input
DCLK
DCLKis provided by the FPGA. This signal provides the timing of the
serial interface. The data presented on ASDIis latched to the serial
configuration device, at the rising edge of DCLK. Data on the DATA
pin changes after the falling edge of DCLKand is latched into the
FPGA on the rising edge.
VCC
GND
3, 7, 8
4
Power
Power pins connect to 3.3 V.
Ground pin.
Ground
Altera Corporation
July 2004
Core Version a.b.c variable
4–31
Configuration Handbook, Volume 2
ALTERA [ ALTERA CORPORATION ]
