Duty Cycle Distortion
Table 5–82. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3
Devices
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO Clock Port
(No PLL in Clock Path)
Row DDIO Output I/O
Standard
LVDS/
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL HyperTransport
Technology
3.3 & 2.5 V 1.8 & 1.5 V
2.5 V
1.8 & 1.5 V
3.3 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
260
210
195
150
255
175
170
155
150
150
180
380
330
315
265
370
295
290
275
270
270
180
145
100
85
145
100
85
110
65
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
75
1.8 V
85
85
120
105
70
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
140
65
140
65
60
60
75
55
50
90
60
60
95
55
55
90
LVDS/ HyperTransport
technology
180
180
180
Notes to Table 5–82:
(1) The information in Table 5–82 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Here is an example for calculating the DCD in percentage for a DDIO
output on a row I/O on a -3 device:
If the input I/O standard is SSTL-2 and the DDIO output I/O standard is
SSTL-2 Class II, the maximum DCD is 60 ps (see Table 5–82). If the clock
frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3745 ps
Calculate the DCD as a percentage:
(T/2 – DCD) / T = (3745ps/2 – 60ps) / 3745ps = 48.4% (for low
boundary)
(T/2 + DCD) / T = (3745 ps/2 + 60 ps) / 3745ps = 51.6% (for high
boundary)
5–82
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
