DC & Switching Characteristics
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 2 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL
1.8/1.5 V
3.3/2.5 V
1.8/1.5 V
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
335
320
330
330
330
330
420
180
390
375
385
385
390
360
470
180
65
70
65
80
ps
ps
ps
ps
ps
ps
ps
ps
60
70
60
70
60
70
90
100
165
180
155
180
LVPECL
Note to Table 5–85:
(1) Table 5–85 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 1 of 2)
Note (1)
Maximum DCD (PLL Output Clock Feeding
DDIO Clock Port)
Row DDIO Output I/O
Standard
Unit
-3 Device
-4 & -5 Device
3.3-V LVTTL
3.3-V LVCMOS
2.5V
110
65
105
75
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
75
90
1.8V
85
100
100
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
105
65
60
50
50
70
65
70
55
70
Altera Corporation
May 2007
5–85
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
