Duty Cycle Distortion
Table 5–84. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3
Devices (Part 2 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
1.2-V
HSTL
Unit
TTL/CMOS
SSTL-2
SSTL/HSTL
3.3/2.5 V
1.8/1.5 V
2.5 V
1.8/1.5 V
1.2 V
1.8 V
150
255
175
170
155
140
150
150
150
125
240
180
265
370
295
290
275
260
270
270
270
240
360
180
85
140
65
85
140
65
85
140
65
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
60
60
60
55
50
50
70
70
70
60
60
60
60
60
60
55
55
55
85
85
85
155
180
155
180
155
180
LVPECL
Note to Table 5–84:
(1) Table 5–84 assumes the input clock has zero DCD.
(2) The DCD specification is based on a no logic array noise condition.
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 1 of 2)
Notes (1), (2)
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
Clock Port (No PLL in the Clock Path)
DDIO Column Output I/O
Standard
Unit
TTL/CMOS
SSTL-2
2.5 V
SSTL/HSTL
1.8/1.5 V
3.3/2.5 V
1.8/1.5 V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
440
390
375
325
430
355
350
495
450
430
385
490
410
405
170
120
105
90
160
110
95
ps
ps
ps
ps
ps
ps
ps
1.8 V
100
155
75
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
160
85
80
70
5–84
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
