Disabling IEEE Std. 1149.1 BST Circuitry
The IEEE Std. 1149.1 BST circuitry for Cyclone II devices is enabled upon
Disabling IEEE
Std. 1149.1 BST
Circuitry
device power-up. Because this circuitry may be used for BST or in-circuit
reconfiguration, this circuitry must be enabled only at specific times as
mentioned in “Using IEEE Std. 1149.1 BST Circuitry” on page 14–16.
If the IEEE Std. 1149.1 circuitry will not be utilized at any time, the
circuitry should be permanently disabled. Table 14–3 shows the pin
connections necessary for disabling the IEEE Std. 1149.1 circuitry in
Cyclone II devices to ensure that the circuitry is not inadvertently enabled
when it is not needed.
Table 14–3. Disabling IEEE Std. 1149.1 Circuitry
JTAG Pins (1)
TMS
Connection for Disabling
VCC
GND
TCK
VCC
TDI
Leave open
TDO
Note to Table 14–3:
(1) There is no software option to disable JTAG in Cyclone II devices. The JTAG pins
are dedicated.
Use the following guidelines when performing boundary-scan testing
with IEEE Std. 1149.1 devices:
Guidelines for
IEEE Std. 1149.1
Boundary-Scan
Testing
■
If the 10-bit checkerboard pattern “1010101010” does not shift out of
the instruction register via the TDOpin during the first clock cycle of
the SHIFT_IRstate, the TAP controller has not reached the proper
state. To solve this problem, try one of the following procedures:
●
Verify that the TAP controller has reached the SHIFT_IRstate
correctly. To advance the TAP controller to the SHIFT_IRstate,
return to the RESETstate and send the code 01100to the TMS
pin.
●
Check the connections to the VCC, GND, JTAG, and dedicated
configuration pins on the device.
14–18
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
