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EP2C8T144I8N 参数 Datasheet PDF下载

EP2C8T144I8N图片预览
型号: EP2C8T144I8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑时钟
文件页数/大小: 470 页 / 5765 K
品牌: ALTERA [ ALTERA CORPORATION ]
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IEEE 1149.1 (JTAG) Boundary-Scan Testing for Cyclone II Devices  
Perform a SAMPLE/PRELOADtest cycle prior to the first EXTESTtest  
cycle to ensure that known data is present at the device pins when  
the EXTESTmode is entered. If the OEJupdate register contains a 0,  
the data in the OUTJupdate register is driven out. The state must be  
known and correct to avoid contention with other devices in the  
system.  
Do not perform EXTESTtesting during ICR. This instruction is  
supported before or after ICR, but not during ICR. Use the  
CONFIG_IOinstruction to interrupt configuration, then perform  
testing, or wait for configuration to complete.  
If performing testing before configuration, hold the nCONFIGpin  
low.  
After configuration, any pins in a differential pin pair cannot be  
tested. Therefore, performing BST after configuration requires  
editing BSC group definitions that correspond to these differential  
pin pairs. The BSC group should be redefined as an internal cell. See  
the BSDL file for more information on editing.  
For more information on boundary scan testing, contact Altera  
Applications.  
The Boundary-Scan Description Language (BSDL), a subset of VHDL,  
provides a syntax that allows you to describe the features of an  
IEEE Std. 1149.1 BST-capable device that can be tested. Test software  
development systems then use the BSDL files for test generation,  
analysis, and failure diagnostics. For more information, or to receive  
BSDL files for IEEE Std. 1149.1-compliant Cyclone II devices, visit the  
Altera web site at www.altera.com.  
Boundary-Scan  
Description  
Language  
(BSDL) Support  
The IEEE Std. 1149.1 BST circuitry available in Cyclone II devices  
provides a cost-effective and efficient way to test systems that contain  
devices with tight lead spacing. Circuit boards with Altera and other  
IEEE Std. 1149.1-compliant devices can use the EXTEST,  
SAMPLE/PRELOAD, BYPASS,IDCODE,USERCODE,CLAMP,and HIGHZ  
modes to create serial patterns that internally test the pin connections  
between devices and check device operation.  
Conclusion  
References  
Bleeker, H., P. van den Eijnden, and F. de Jong. Boundary-Scan Test: A  
Practical Approach. Eindhoven, The Netherlands: Kluwer Academic  
Publishers, 1993.  
Institute of Electrical and Electronics Engineers, Inc. IEEE Standard Test  
Access Port and Boundary-Scan Architecture (IEEE Std 1149.1-2001). New  
York: Institute of Electrical and Electronics Engineers, Inc., 2001.  
Altera Corporation  
February 2007  
14–19  
Cyclone II Device Handbook, Volume 1  
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