Cyclone II Architecture
Figure 2–3. LE in Normal Mode
sload
sclear
(LAB Wide) (LAB Wide)
Packed Register Input
Register chain
connection
Row, Column, and
Direct Link Routing
Q
D
data1
data2
Row, Column, and
Direct Link Routing
ENA
Four-Input
LUT
data3
cin (from cout
of previous LE)
CLRN
clock (LAB Wide)
Local routing
data4
ena (LAB Wide)
aclr (LAB Wide)
Register
chain output
Register Feedback
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters,
accumulators, and comparators. An LE in arithmetic mode implements a
2-bit full adder and basic carry chain (see Figure 2–4). LEs in arithmetic
mode can drive out registered and unregistered versions of the LUT
output. Register feedback and register packing are supported when LEs
are used in arithmetic mode.
Altera Corporation
February 2007
2–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
