Cyclone II Architecture
This gives a maximum of seven control signals at a time. When using the
LAB-wide synchronous load, the clkena of labclk1 is not available.
Additionally, register packing and synchronous load cannot be used
simultaneously.
Each LAB can have up to four non-global control signals. Additional LAB
control signals can be used as long as they are global signals.
Synchronous clear and load signals are useful for implementing counters
and other functions. The synchronous clear and synchronous load signals
are LAB-wide signals that affect all registers in the LAB.
Each LAB can use two clocks and two clock enable signals. Each LAB’s
clock and clock enable signals are linked. For example, any LE in a
particular LAB using the labclk1 signal also uses labclkena1. If the
LAB uses both the rising and falling edges of a clock, it also uses both
LAB-wide clock signals. De-asserting the clock enable signal turns off the
LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-
wide control signals. The MultiTrack™ interconnect’s inherent low skew
allows clock and control signal distribution in addition to data. Figure 2–7
shows the LAB control signal generation circuit.
Figure 2–7. LAB-Wide Control Signals
Dedicated
LAB Row
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
labclkena2
labclkena1
labclr1
synclr
labclk1
labclk2
syncload
labclr2
LAB-wide signals control the logic for the register’s clear signal. The LE
directly supports an asynchronous clear function. Each LAB supports up
to two asynchronous clear signals (labclr1and labclr2).
Altera Corporation
February 2007
2–9
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
