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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

EP2C50A15Q324C6ES图片预览
型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2. CycloneII Architecture  
CII51002-3.1  
Cyclone® II devices contain a two-dimensional row- and column-based  
architecture to implement custom logic. Column and row interconnects  
of varying speeds provide signal interconnects between logic array  
blocks (LABs), embedded memory blocks, and embedded multipliers.  
Functional  
Description  
The logic array consists of LABs, with 16 logic elements (LEs) in each  
LAB. An LE is a small unit of logic providing efficient implementation of  
user logic functions. LABs are grouped into rows and columns across the  
device. Cyclone II devices range in density from 4,608 to 68,416 LEs.  
Cyclone II devices provide a global clock network and up to four  
phase-locked loops (PLLs). The global clock network consists of up to 16  
global clock lines that drive throughout the entire device. The global clock  
network can provide clocks for all resources within the device, such as  
input/output elements (IOEs), LEs, embedded multipliers, and  
embedded memory blocks. The global clock lines can also be used for  
other high fan-out signals. Cyclone II PLLs provide general-purpose  
clocking with clock synthesis and phase shifting as well as external  
outputs for high-speed differential I/O support.  
M4K memory blocks are true dual-port memory blocks with 4K bits of  
memory plus parity (4,608 bits). These blocks provide dedicated true  
dual-port, simple dual-port, or single-port memory up to 36-bits wide at  
up to 260 MHz. These blocks are arranged in columns across the device  
in between certain LABs. Cyclone II devices offer between 119 to  
1,152 Kbits of embedded memory.  
Each embedded multiplier block can implement up to either two 9 × 9-bit  
multipliers, or one 18 × 18-bit multiplier with up to 250-MHz  
performance. Embedded multipliers are arranged in columns across the  
device.  
Each Cyclone II device I/O pin is fed by an IOE located at the ends of LAB  
rows and columns around the periphery of the device. I/O pins support  
various single-ended and differential I/O standards, such as the 66- and  
33-MHz, 64- and 32-bit PCI standard, PCI-X, and the LVDS I/O standard  
at a maximum data rate of 805 megabits per second (Mbps) for inputs and  
640 Mbps for outputs. Each IOE contains a bidirectional I/O buffer and  
three registers for registering input, output, and output-enable signals.  
Dual-purpose DQS, DQ, and DM pins along with delay chains (used to  
Altera Corporation  
February 2007  
2–1  
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