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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

EP2C50A15Q324C6ES图片预览
型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Logic Elements  
phase-align double data rate (DDR) signals) provide interface support for  
external memory devices such as DDR, DDR2, and single data rate (SDR)  
SDRAM, and QDRII SRAM devices at up to 167 MHz.  
Figure 2–1 shows a diagram of the Cyclone II EP2C20 device.  
Figure 2–1. Cyclone II EP2C20 Device Block Diagram  
PLL  
IOEs  
PLL  
Embedded  
Multipliers  
Logic  
Array  
Logic  
Array  
Logic  
Array  
Logic  
Array  
IOEs  
IOEs  
M4K Blocks  
M4K Blocks  
PLL  
IOEs  
PLL  
The number of M4K memory blocks, embedded multiplier blocks, PLLs,  
rows, and columns vary per device.  
The smallest unit of logic in the Cyclone II architecture, the LE, is compact  
and provides advanced features with efficient logic utilization. Each LE  
features:  
Logic Elements  
A four-input look-up table (LUT), which is a function generator that  
can implement any function of four variables  
A programmable register  
A carry chain connection  
A register chain connection  
The ability to drive all types of interconnects: local, row, column,  
register chain, and direct link interconnects  
Support for register packing  
Support for register feedback  
2–2  
Altera Corporation  
Cyclone II Device Handbook, Volume 1  
February 2007  
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