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EP2C50A15Q324C6ES 参数 Datasheet PDF下载

EP2C50A15Q324C6ES图片预览
型号: EP2C50A15Q324C6ES
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件系列 [Cyclone II Device Family]
分类和应用:
文件页数/大小: 168 页 / 2205 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Introduction  
Vertical migration means that you can migrate to devices whose  
dedicated pins, configuration pins, and power pins are the same for a  
given package across device densities.  
Table 1–3. Total Number of Non-Migratable I/O Pins for Cyclone II Vertical Migration Paths  
256-Pin  
FineLineBGA FineLineBGA  
484-Pin  
672-Pin  
FineLineBGA  
(3)  
Vertical  
Migration Path  
208-Pin  
PQFP  
484-Pin Ultra  
FineLine BGA  
144-Pin TQFP  
(1)  
(2)  
EP2C5 to  
EP2C8  
4
4
1 (4)  
28  
28  
EP2C8 to  
EP2C15  
30  
0
0
EP2C15 to  
EP2C20  
EP2C20 to  
EP2C35  
16  
28  
EP2C35 to  
EP2C50  
28 (5)  
28  
EP2C50 to  
EP2C70  
Notes to Table 1–3:  
(1) Vertical migration between the EP2C5F256 to the EP2C15AF256 and the EP2C5F256 to the EP2C20F256 devices is  
not supported.  
(2) When migrating from the EP2C20F484 device to the EP2C50F484 device, a total of 39 I/O pins are non-migratable.  
(3) When migrating from the EP2C35F672 device to the EP2C70F672 device, a total of 56 I/O pins are non-migratable.  
(4) In addition to the one non-migratable I/O pin, there are 34 DQ pins that are non-migratable.  
(5) The pinouts of 484 FBGA and 484 UBGA are the same.  
1
When moving from one density to a larger density, I/O pins are  
often lost because of the greater number of power and ground  
pins required to support the additional logic within the larger  
device. For I/O pin migration across densities, you must cross  
reference the available I/O pins using the device pin-outs for all  
planned densities of a given package type to identify which I/O  
pins are migratable.  
To ensure that your board layout supports migratable densities within  
one package offering, enable the applicable vertical migration path  
within the Quartus II software (go to Assignments menu, then Device,  
then click the Migration Devices button). After compilation, check the  
information messages for a full list of I/O, DQ, LVDS, and other pins that  
are not available because of the selected migration path. Table 1–3 lists the  
Cyclone II device package offerings and shows the total number of  
non-migratable I/O pins when migrating from one density device to a  
larger density device.  
Altera Corporation  
February 2008  
1–7  
Cyclone II Device Handbook, Volume 1  
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