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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure & Features  
Figure 2–20. Cyclone II IOE Structure  
Logic Array  
OE Register  
OE  
Output Register  
Output  
Input (1)  
Input Register  
Note to Figure 2–20:  
(1) There are two paths available for combinational or registered inputs to the logic  
array. Each path contains a unique programmable delay chain.  
The IOEs are located in I/O blocks around the periphery of the Cyclone II  
device. There are up to five IOEs per row I/O block and up to four IOEs  
per column I/O block (column I/O blocks span two columns). The row  
I/O blocks drive row, column (only C4 interconnects), or direct link  
interconnects. The column I/O blocks drive column interconnects.  
Figure 2–21 shows how a row I/O block connects to the logic array.  
Figure 2–22 shows how a column I/O block connects to the logic array.  
2–38  
Cyclone II Device Handbook, Volume 1  
Altera Corporation  
February 2007