Cyclone II Architecture
There are five dynamic control input signals that feed the embedded
multiplier:
signa, signb, clk, clkena,
and
aclr. signa
and
signb
can be registered to match the data signal input path. The same
clk,
clkena,
and
aclr
signals feed all registers within a single embedded
multiplier.
f
For more information on Cyclone II embedded multipliers, see the
Embedded Multipliers in Cyclone II Devices
chapter.
IOEs support many features, including:
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I/O Structure &
Features
Differential and single-ended I/O standards
3.3-V, 64- and 32-bit, 66- and 33-MHz PCI compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) support
Output drive strength control
Weak pull-up resistors during configuration
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors in user mode
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
V
REF
pins
Cyclone II device IOEs contain a bidirectional I/O buffer and three
registers for complete embedded bidirectional single data rate transfer.
Figure 2–20
shows the Cyclone II IOE structure. The IOE contains one
input register, one output register, and one output enable register. You can
use the input registers for fast setup times and output registers for fast
clock-to-output times. Additionally, you can use the output enable (OE)
register for fast clock-to-output enable timing. The Quartus II software
automatically duplicates a single OE register that controls multiple
output or bidirectional pins. You can use IOEs as input, output, or
bidirectional pins.
Altera Corporation
February 2007
2–37
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
