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EP2C35F672C8N 参数 Datasheet PDF下载

EP2C35F672C8N图片预览
型号: EP2C35F672C8N
PDF下载: 下载PDF文件 查看货源
内容描述: Cyclone II器件手册,卷1 [Cyclone II Device Handbook, Volume 1]
分类和应用: 现场可编程门阵列可编程逻辑LTE时钟
文件页数/大小: 470 页 / 5764 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Cyclone II Architecture  
Embedded multipliers can operate at up to 250 MHz (for the fastest speed  
grade) for 18 × 18 and 9 × 9 multiplications when using both input and  
output registers.  
Each Cyclone II device has one to three columns of embedded multipliers  
that efficiently implement multiplication functions. An embedded  
multiplier spans the height of one LAB row. Table 2–10 shows the number  
of embedded multipliers in each Cyclone II device and the multipliers  
that can be implemented.  
Table 2–10. Number of Embedded Multipliers in Cyclone II Devices  
Note (1)  
Embedded  
Multiplier Columns  
Embedded  
Multipliers  
Device  
9 × 9 Multipliers 18 × 18 Multipliers  
EP2C5  
EP2C8  
1
1
1
1
1
2
3
13  
18  
26  
36  
13  
18  
EP2C15  
EP2C20  
EP2C35  
EP2C50  
EP2C70  
26  
52  
26  
26  
52  
26  
35  
70  
35  
86  
172  
300  
86  
150  
150  
Note to Table 2–10:  
(1) Each device has either the number of 9 × 9-, or 18 × 18-bit multipliers shown. The total number of multipliers for  
each device is not the sum of all the multipliers.  
The embedded multiplier consists of the following elements:  
Multiplier block  
Input and output registers  
Input and output interfaces  
Figure 2–18 shows the multiplier block architecture.  
Altera Corporation  
February 2007  
2–33  
Cyclone II Device Handbook, Volume 1