PLLs in Cyclone II Devices
You can use the altpllmegafunction in the Quartus II software to
enable Cyclone II PLLs. Figure 7–3 shows the available ports in
Cyclone II PLLs and their sources and destinations. The c0 and c1
counters feed the internal global clock networks and the c2 counter can
feed the global clock network and a dedicated external clock output pin
(PLL<#>_OUT) at the same time.
Software
Overview
Figure 7–3. Cyclone II PLL Signals
(1)
inclk[1..0] (2)
pllena
c[1..0]
(3) c2
locked
areset
pfdena
clkswitch
Physical Pins
Signal driven by internal logic
Signal driven to internal logic
Internal clock signal
Physical pins and internal clock signal
Notes to Figure 7–3:
(1) These signals can be assigned to either a single-ended or differential I/O standard.
(2) The inclkmust be driven by one of two dedicated clock input pins.
(3) This counter output can drive both a dedicated external clock output
(PLL<#>_OUT) and the global clock network.
Altera Corporation
February 2007
7–7
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
