Software Overview
Tables 7–4 and 7–5 describe the Cyclone II PLL input and output ports.
Table 7–4. PLL Input Signals
Port
Description
Source
Destination
Primary and secondary clock inputs to the PLL.
Dedicated clock
input pins
n counter
inclk[1..0]
Logic array or
input pin
PLL control signal
pllena
pllenais an active high signal that acts as an
enable and reset signal for the PLL. It can be used
for enabling or disabling each PLL. When
pllenatransitions low, the PLL clock output
ports are driven to GND and the PLL loses lock.
Once pllenatransitions high again, the lock
process begins and the PLL re-synchronizes to its
input reference clock. The pllenaport can be
driven by an LE output or any general-purpose I/O
pin.
Logic array or
input pin
PLL control signal
areset
pfdena
aresetis an active high signal that resets all PLL
counters to their initial values. When this signal is
driven high the PLL resets its counters, clears the
PLL outputs and loses lock. Once this signal is
driven low again, the lock process begins and the
PLL re-synchronizes to its input reference clock.
The aresetport can be driven by an LE output
or any general-purpose I/O pin.
Logic array or
input pin
PFD
pfdenais an active high signal that enables or
disables the up/down output signals from the
PFD. When pfdenais driven low, the PFD is
disabled, while the VCO continues to operate. The
PLL clock outputs continue to toggle regardless of
the input clock, but may experience some long-
term drift. Because the output clock frequency
does not change for some time, you can use the
pfdenaport as a shutdown or cleanup function
when a reliable input clock is no longer available.
The pfdenaport can be driven by an LE output
or any general-purpose I/O pin.
Logic array or
input pin
PLL control signal
clkswitch
clkswitchis an active high switchover signal
used to initiate manual clock switchover.
7–8
Altera Corporation
February 2007
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
