PLLs in Cyclone II Devices
Figure 7–2. Cyclone II PLL Block Diagram
VCO Phase Selection
Selectable at Each
PLL Output Port
Post-Scale
Counters
Manual Clock
Switchover
Select Signal
8
Reference
Input Clock
Global
Clock
÷c0
f
= f /n
REF IN
f
VCO
CLK0 (1)
up
8
inclk0
inclk1
CLK1
f
Global
Clock
Charge
Pump
IN
Loop
Filter
÷n
PFD
VCO
÷k
(3)
÷c1
CLK2 (1)
down
CLK3
8
f
FB
÷c2
(2)
Global
Clock
÷m
PLL<#>_OUT
To I/O or
general routing
Lock Detect
& Filter
Notes to Figure 7–2:
(1) This input can be single-ended or differential. If you are using a differential I/O standard, then the design uses two
clock pins. LVDS input is supported via the secondary function of the dedicated clock pins. For example, the CLK0
pin’s secondary function is LVDSCLK1pand the CLK1pin’s secondary function is LVDSCLK1n. Figure 7–2 shows
the possible clock input connections to PLL 1.
(2) This counter output is shared between a dedicated external clock output (PLL<#>_OUT) and the global clock
network.
(3) If the VCO post scale counter = 2, a 300- to 500-MHz internal VCO frequency is available.
The Cyclone II PLL supports up to three global clock outputs and one
dedicated external clock output. The output frequency to the global clock
network or dedicated external clock output is determined by using the
following equation:
m
f
= f
IN
global/external
n × C
fIN is the clock input to the PLL and C is the setting on the c0, c1, or c2
counter.
The VCO frequency is determined in all cases by using the following
equation:
m
f
= f
IN
VCO
n
Altera Corporation
February 2007
7–5
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
