PLLs in Cyclone II Devices
Table 7–5. PLL Output signals
Port
Description
Source
Destination
PLL clock outputs driving the internal global clock PLL post-scale
Global clock
network or
c[2..0]
network or external clock output pin
counter
external I/O pin
(PLL<#>_OUT)
Locked
Gives the status of the PLL lock. When the PLL is PLL lock detect
locked, this port drives VCC. When the PLL is out circuit
of lock, this port drives GND. The locked port may
Logic array or
output pin
pulse high and low during the PLL lock process.
Table 7–6 shows a list of I/O standards supported in Cyclone II device
PLLs.
Table 7–6. I/O Standards Supported for Cyclone II PLLs (Part 1 of 2)
Input
inclk
v
Output
I/O Standard
lock
pll_out
LVTTL (3.3, 2.5, and 1.8 V)
v
v
v
v
LVCMOS (3.3, 2.5, 1.8, and
1.5 V)
v
3.3-V PCI
3.3-V PCI-X (1)
LVPECL
v
v
v
v
v
v
v
v
LVDS
v
v
1.5 and 1.8 V differential
HSTL class I and class II
v (2)
v
1.8 and 2.5 V differential
SSTL class I and class II
v (2)
v
1.5-V HSTL class I
1.5-V HSTL class II (3)
1.8-V HSTL class I
1.8-V HSTL class II (3)
SSTL-18 class I
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
SSTL-18 class II (3)
SSTL-25 class I
Altera Corporation
February 2007
7–9
Cyclone II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
