Figure 2–1. Stratix GX Transceiver Block
Note (1)
Receiver Channel 0
Channel 0
Receiver Pins
PLD
Logic
Array
Transmitter Channel 0
Transmitter Pins
Receiver Channel 1
Channel 1
Receiver Pins
PLD
Logic
Array
Transmitter Channel 1
Transmitter Pins
PLD
Logic
Array
XAUI
PLD
XAUI
Transmitter
State
Channel
Aligner
State
Transmitter
PLL
Receiver
State
Logic
Array
(2)
Machine
Machine
Machine
Receiver Pins
Receiver Channel 2
PLD
Logic
Array
Channel 2
Transmitter Pins
Transmitter Channel 2
Receiver Pins
Receiver Channel 3
Channel 3
PLD
Logic
Array
Transmitter Pins
Transmitter Channel 3
Notes to Figure 2–1:
(1) Each receiver channel has its own PLL and CRU, which are not shown in this diagram. For more information, refer
to the section “Receiver Path” on page 2–13.
(2) For possible transmitter PLL clock inputs, refer to the section “Transmitter Path” on page 2–5.
2–2
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
