DC & Switching Characteristics
The scaling factors for output pin timing in Table 6–80 are shown in units
of time per pF unit of capacitance (ps/pF). Add this delay to the
combinational timing path for output or bidirectional pins in addition to
the “I/O Adder” delays shown in Tables 6–72 through 6–77 and the “IOE
Programmable Delays” in Tables 6–78 and 6–79.
Table 6–80. Output Delay Adder for Loading on LVTTL/LVCMOS Output Buffers
LVTTL/LVCMOS Standards
Output Pin Adder Delay (ps/pF)
Conditions
Parameter
3.3-V LVTTL 2.5-V LVTTL 1.8-V LVTTL 1.5-V LVTTL
LVCMOS
Value
24 mA
16 mA
12 mA
8 mA
15
25
30
50
60
–
–
–
–
-
–
8
18
25
35
–
–
25
40
–
–
15
20
30
60
Drive Strength
35
80
160
4 mA
2 mA
75
120
SSTL/HSTL Standards
Output Pin Adder Delay (ps/pF)
Conditions
SSTL-3
25
SSTL-2
25
SSTL-1.8
1.5-V HSTL 1.8-V HSTL
Class I
Class II
25
25
25
20
25
20
25
20
GTL+/GTL/CTT/PCI Standards
Output Pin Adder Delay (ps/pF)
Conditions
GTL+
GTL
CTT
PCI
AGP
Parameter
Value
VCCIO voltage
level
3.3 V
2.5 V
18
15
18
18
25
-
20
-
20
-
Altera Corporation
June 2006
6–53
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
