Timing Model
Table 6–77. Stratix GX I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
4 mA
8 mA
12 mA
4 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
16 mA
2 mA
8 mA
12 mA
2 mA
4 mA
8 mA
1,930
1,930
1,710
1,490
1,953
1,733
1,513
1,453
2,632
2,052
1,942
1,902
4,537
3,447
3,377
6,575
5,995
5,525
1,410
1,450
1,310
1,797
1,717
1,340
1,400
1,300
1,430
2,031
2,031
1,800
1,569
2,055
1,824
1,593
1,530
2,769
2,160
2,044
2,002
4,773
3,628
3,555
6,917
6,308
5,815
1,485
1,527
1,380
1,892
1,808
1,411
1,474
1,369
1,506
2,335
2,335
2,069
1,803
2,363
2,097
1,831
1,759
3,183
2,483
2,350
2,301
5,489
4,172
4,088
7,954
7,253
6,686
1,707
1,755
1,586
2,175
2,079
1,622
1,694
1,573
1,731
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
CTT
SSTL-3 class I
SSTL-3 class II
SSTL-2 class I
SSTL-2 class II
LVDS (1)
LVPECL (1)
3.3-V PCML (1)
HyperTransport technology (1)
Note to Tables 6–72 through 6–77:
(1) These parameters are only available on the left side row I/O pins.
6–50
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
