DC & Switching Characteristics
Tables 6–78 and 6–79 show the adder delays for the column and row IOE
programmable delays, respectively. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
Table 6–78. Stratix GX IOE Programmable Delays on Column Pins
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Parameter
Setting
Unit
Min
Max
Min
Max
Min
Max
Decrease input delay to
internal cells
Off
3,970
3,390
2,810
212
212
3900
0
4,367
3,729
3,091
224
224
4,290
0
5,022
4,288
3,554
257
257
4,933
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
On
Small
Medium
Large
Off
Decrease input delay to
input register
On
Decrease input delay to
output register
Off
1,240
0
1,364
0
1,568
0
On
Increase delay to output
pin
Off
0
0
0
On
377
0
397
0
456
0
Increase delay to output
enable pin
Off
On
338
0
372
0
427
0
Increase output clock
enable delay
Off
On
540
1,016
1,016
0
594
1,118
1,118
0
683
1,285
1,285
0
Small
Large
Increaseinputclockenable Off
delay
On
Small
540
1,016
1,016
0
594
1,118
1,118
0
683
1,285
1,285
0
Large
Off
Increase output enable
clock enable delay
On
540
1,016
1,016
594
1,118
1,118
683
1,285
1,285
Small
Large
Altera Corporation
June 2006
6–51
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
