Timing Model
Table 6–73. Stratix GX I/O Standard Row Pin Input Delay Adders (Part 2 of 2)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
I/O Standard
Unit
Min
Max
Min
Max
Min
Max
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
LVDS (1)
0
0
0
ps
ps
ps
ps
ps
ps
ps
70
73
83
70
73
83
40
42
48
LVPECL (1)
–50
330
80
–53
346
84
–61
397
96
3.3-V PCML (1)
HyperTransport (1)
Table 6–74. Stratix GX I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
Standard
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
4 mA
570
570
350
130
0
599
599
368
137
0
689
689
423
157
0
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
8 mA
12 mA
24 mA
4 mA
3.3-V LVTTL
2.5-V LVTTL
570
350
130
70
599
368
137
74
689
423
157
85
8 mA
12 mA
16 mA
24 mA
2 mA
0
0
0
830
250
140
100
420
350
350
1,740
1,160
690
–150
872
263
147
105
441
368
368
1,827
1,218
725
–157
1,002
302
169
120
507
423
423
2,101
1,400
833
–181
8 mA
12 mA
16 mA
2 mA
1.8-V LVTTL
1.5-V LVTTL
8 mA
12 mA
2 mA
4 mA
8 mA
GTL
6–46
Altera Corporation
June 2006
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
