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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Transceivers  
Figure 2–12. External Termination & Biasing Circuit  
Receiver External Termination  
and Biasing  
Stratix GX Device  
V
DD  
50/60/75-Ω  
Termination  
Resistance  
R1  
C1  
Receiver  
R1/R2 = 1K  
× {R2/(R1 + R 2)} = 1.1 V  
RXIP  
V
R2  
DD  
RXIN  
Receiver External Termination  
and Biasing  
Transmission  
Line  
Programmable Equalizer  
The programmable equalizer module boosts the high frequency  
components of the incoming signal to compensate for losses in the  
transmission medium. There are five possible equalization settings (0, 1,  
2, 3, 4) to compensate for 0”, 10”, 20”, 30”, and 40” of FR4 trace. These  
settings should be interpreted loosely. The programmable equalizer can  
be set dynamically or statically.  
Receiver PLL & CRU  
Each transceiver block has four receiver PLLs and CRUs, each of which is  
dedicated to a receive channel. If the receive channel associated with a  
particular receiver PLL or CRU is not used, then the receiver PLL or CRU  
is powered down for the channel. Figure 2–13 is a diagram of the receiver  
PLL and CRU circuits.  
Altera Corporation  
June 2006  
2–15  
Stratix GX Device Handbook, Volume 1  
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