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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Figure 2–10 shows a diagram of the receiver input buffer, which contains:  
Programmable termination  
Programmable equalizer  
Figure 2–10. Receiver Input Buffer  
Programmable  
Termination  
Input  
Pins  
Programmable  
Equalizer  
Differential  
Input  
Buffer  
Programmable Termination  
The programmable termination can be statically set in the Quartus II  
software. Figure 2–11 shows the setup for programmable receiver  
termination.  
Figure 2–11. Programmable Receiver Termination  
Differential  
Input  
Buffer  
50, 60, or 75 Ω  
V
CM  
50, 60, or 75 Ω  
If you use external termination, then the receiver must be externally  
terminated and biased to 1.1 V. Figure 2–12 shows an example of an  
external termination/biasing circuit.  
2–14  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
June 2006  
 
 
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