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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Deserializer (Serial-to-Parallel Converter)  
The deserializer converts the serial stream into a parallel 8- or 10-bit data  
bus. The deserializer receives the least significant bit first. Figure 2–14 is  
a diagram of the deserializer.  
Figure 2–14. Deserializer  
D9  
D9  
D8  
D7  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
10  
High-speed  
serial clock  
Low-speed  
parallel clock  
Word Aligner  
The word aligner aligns the incoming data based on the specific byte  
boundaries. The word aligner has three customizable modes of operation:  
bit-slip mode, 16-bit mode, and 10-bit mode, the last of which is available  
for the basic and SONET modes. The word aligner also has two  
non-customizable modes of operation, which are the XAUI and GIGE  
modes.  
Figure 2–15 shows the word aligner in bit-slip mode.  
2–18  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
June 2006  
 
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