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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Transceivers  
Figure 2–15. Word Aligner in Bit-Slip Mode  
Word Aligner  
Manual  
Alignment  
Mode  
Patterm Detector  
Bit-Slip  
Mode  
10-Bit  
Mode  
16-Bit  
Mode  
7-Bit  
Mode  
A1A2  
Mode  
A1A1A2A2  
Mode  
In the bit-slip mode, the byte boundary can be modified by a barrel shifter  
to slip the byte boundary one bit at a time via a user-controlled bit-slip  
port. The bit-slip mode supports both 8-bit and 10-bit data paths  
operating in a single or double-width mode.  
The pattern detector is active in the bit-slip mode, and it detects the  
user-defined pattern that is specified in the MegaWizard® Plug-In  
Manager.  
The bit-slip mode is available only in Custom mode and SONET mode.  
Figure 2–16 shows the word aligner in 16-bit mode.  
Altera Corporation  
June 2006  
2–19  
Stratix GX Device Handbook, Volume 1  
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