Figure 2–5. Serializer
D9
D8
D7
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
10
Serial data
out (to output
buffer)
Low-speed
parallel clock
High-speed
serial clock
Transmit Buffer
The Stratix GX transceiver buffers support the 1.5-V pseudo current
mode logic (PCML) I/O standard at a rate up to 3.1875 Gbps, across up to
40 inches of FR4 trace, and across 2 connectors. Additional I/O standards,
LVDS, 3.3-V PCML, LVPECL, can be supported when AC coupled. The
common mode of the output driver is 750 mV.
The output buffer, as shown in Figure 2–6, consists of a programmable
output driver and a programmable pre-emphasis circuit.
2–10
Stratix GX Device Handbook, Volume 1
Altera Corporation
June 2006