欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第159页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第160页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第161页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第162页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第164页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第165页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第166页浏览型号EP1SGX40GF1020I6的Datasheet PDF文件第167页  
Stratix GX Architecture  
Figure 4–58. Stratix GX IOE Structure  
Logic Array  
OE Register  
D
Q
OE  
OE Register  
D
Q
Output Register  
D
Q
Output A  
CLK  
Output Register  
D
Q
Output B  
Input Register  
D
Q
Input A  
Input B  
Input Latch  
Input Register  
D
Q
D
Q
ENA  
The IOEs are located in I/O blocks around the periphery of the Stratix GX  
device. There are up to four IOEs per row I/O block and six IOEs per  
column I/O block. The row I/O blocks drive row, column, or direct link  
interconnects. The column I/O blocks drive column interconnects.  
Figure 4–59 shows how a row I/O block connects to the logic array.  
Figure 4–60 shows how a column I/O block connects to the logic array.  
Altera Corporation  
February 2005  
4–97  
Stratix GX Device Handbook, Volume 1  
 复制成功!