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EP1SGX40GF1020I6 参数 Datasheet PDF下载

EP1SGX40GF1020I6图片预览
型号: EP1SGX40GF1020I6
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 272 页 / 1348 K
品牌: ALTERA [ ALTERA CORPORATION ]
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I/O Structure  
Phase Shifting  
Stratix GX device fast PLLs have advanced clock shift capability that  
enables programmable phase shifts. You can enter a phase shift (in  
degrees or time units) for each PLL clock output port or for all outputs  
together in one shift. You can perform phase shifting in time units with a  
resolution range of 150 to 400 ps. This resolution is a function of the VCO  
period.  
Control Signals  
The fast PLL has the same lockoutput, pllenableinput, and areset  
input control signals as the enhanced PLL.  
For more information on high-speed differential I/O support, see the  
High-Speed Source-Synchronous Differential I/O Interfaces in Stratix GX  
Devices chapter of the Stratix GX Device Handbook, Volume 2.  
IOEs provide many features, including:  
I/O Structure  
Dedicated differential and single-ended I/O buffers  
3.3-V, 64-bit, 66-MHz PCI compliance  
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance  
Joint Test Action Group (JTAG) boundary-scan test (BST) support  
Differential on-chip termination for LVDS I/O standard  
Programmable pull-up during configuration  
Output drive strength control  
Slew-rate control  
Tri-state buffers  
Bus-hold circuitry  
Programmable pull-up resistors  
Programmable input and output delays  
Open-drain outputs  
DQ and DQS I/O pins  
Double-data rate (DDR) Registers  
The IOE in Stratix GX devices contains a bidirectional I/O buffer, six  
registers, and a latch for a complete embedded bidirectional single data  
rate or DDR transfer. Figure 4–58 shows the Stratix GX IOE structure. The  
IOE contains two input registers (plus a latch), two output registers, and  
two output enable registers. The design can use both input registers and  
the latch to capture DDR input and both output registers to drive DDR  
outputs. Additionally, the design can use the output enable (OE) register  
for fast clock-to-output enable timing. The negative edge-clocked OE  
register is used for DDR SDRAM interfacing. The Quartus II software  
automatically duplicates a single OE register that controls multiple  
output or bidirectional pins.  
4–96  
Altera Corporation  
Stratix GX Device Handbook, Volume 1  
February 2005  
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