DC & Switching Characteristics
Table 6–42. Routing Delay Internal Timing Microparameter Descriptions
Symbol
Parameter
tR4
Delay for an R4 line with average loading; covers a distance
of four LAB columns
tR8
Delay for an R8 line with average loading; covers a distance
of eight LAB columns
tR24
tC4
Delay for an R24 line with average loading; covers a distance
of 24 LAB columns
Delay for an C4 line with average loading; covers a distance
of four LAB rows
tC8
Delay for an C8 line with average loading; covers a distance
of eight LAB rows
tC16
Delay for an C16 line with average loading; covers a distance
of 16 LAB rows
tLOCAL
Local interconnect delay
Table 6–43. Stratix GX Reset & PLL Lock Time Parameter Descriptions
Symbol
tANALOGRESETPW
tDIGITALRESETPW
tTX_PLL_LOCK
Parameter
Pulse width to power down analog circuits.
Pulse width to reset digital circuits
The time it takes the tx_pll to lock to the
reference clock.
tRX_FREQLOCK
The time until the clock recovery unit (CRU)
switches to data mode from lock to reference
mode.
tRX_FREQLOCK2PHASELOCK The time until CRU phase locks to data after
switching from lock to data mode.
Figure 6–3 shows the TriMatrix memory waveforms for the M512, M4K,
and M-RAM timing parameters shown in Tables 6–39 through 6–41.
Altera Corporation
August 2005
6–29
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
