DC & Switching Characteristics
Table 6–35. Stratix GX Device Performance (Part 3 of 3)
Notes (1), (2)
Resources Used
Performance
TriMatrix
LEs Memory
Blocks
-5
-6
-7
Applications
DSP
Blocks
Speed Speed Speed Units
Grade Grade Grade
Larger
Designs
8-bit, 16-tap parallel FIR filter
8-bit, 1,024-point FFT function
58
0
5
4
1
141.26 133.49 114.88
261.09 235.51 205.21
MHz
MHz
870
Notes to Table 6–35:
(1) These design performance numbers were obtained using the Quartus II software.
(2) Numbers not listed will be included in a future version of the data sheet.
(3) This application uses registered inputs and outputs.
(4) This application uses registered multiplier input and output stages within the DSP block.
(5) This application uses registered multiplier input, pipeline, and output stages within the DSP block.
Internal Timing Parameters
Internal timing parameters are specified on a speed grade basis
independent of device density. Tables 6–36 through 6–42 describe the
Stratix GX device internal timing microparameters for LEs, IOEs,
TriMatrix™ memory structures, DSP blocks, and MultiTrack
interconnects.
Table 6–36. LE Internal Timing Microparameter Descriptions
Symbol
Parameter
LE register setup time before clock
LE register hold time after clock
LE register clock-to-output delay
LE combinational LUT delay for data-in to data-out
Minimum clear pulse width
tSU
tH
tCO
tLUT
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
Altera Corporation
August 2005
6–25
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
