Timing Model
Table 6–37. IOE Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
tH
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinational output
Column input pin to IOE combinational output
Row IOE data input to combinational output pin
Column IOE data input to combinational output pin
Minimum clear pulse width
tCO
tPIN2COMBOUT_R
tPIN2COMBOUT_C
tCOMBIN2PIN_R
tCOMBIN2PIN_C
tCLR
tPRE
Minimum preset pulse width
tCLKHL
Minimum clock high or low time
Table 6–38. DSP Block Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
tH
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
Input register to DSP block pipeline register in 9 × 9-bit mode
tCO
tINREG2PIPE9
tINREG2PIPE18
Input register to DSP block pipeline register in 18 × 18-bit
mode
tPIPE2OUTREG2ADD
tPIPE2OUTREG4ADD
DSP block pipeline register to output register delay in two-
multipliers adder mode
DSP Block Pipeline Register to output register delay in four-
multipliers adder mode
tPD9
Combinational input to output delay for 9 × 9-bit mode
Combinational input to output delay for 18 × 18-bit mode
Combinational input to output delay for 36 × 36-bit mode
Minimum clear pulse width
tPD18
tPD36
tCLR
tCLKHL
Minimum clock high or low time
6–26
Stratix GX Device Handbook, Volume 1
Altera Corporation
August 2005
ALTERA [ ALTERA CORPORATION ]
