DC & Switching Characteristics
Figure 6–4. Stratix GX Transceiver Reset & PLL Lock Time Waveform Note (1)
tWEREH
tWERESU
rden
tRC
rdaddress
bn
b0
tDATACO1
doutn-1
doutn
reg_data-out
doutn-2
tDATACO2
doutn
doutn-1
unreg_data-out
Note to Figure 6–4:
(1) Waveforms are for minimum pulse width timing and output timing only. Please refer to the Stratix GX Transceiver
User Guide for the complete reset sequence.
Tables 6–44 through 6–50 show the internal timing microparameters for
all Stratix GX devices.
Table 6–44. LE Internal Timing Microparameters
-5 Speed Grade -6 Speed Grade -7 Speed Grade
Symbol
Unit
Min
10
Max
Min
10
Max
Min
11
Max
tSU
ns
ns
ns
ns
ns
ns
ns
tH
100
100
114
tCO
tLUT
tCLR
tPRE
156
366
176
459
202
527
100
100
100
100
100
100
114
114
114
tCLKHL
Altera Corporation
August 2005
6–31
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
