Power Consumption
Table 6–33. Bus Hold Parameters
VCCIO Level
Parameter
Conditions
Units
1.5 V
Max
1.8 V
Max
2.5 V
Max
3.3 V
Max
Min
Min
Min
Min
Low sustaining VIN > VIL
current
25
30
50
70
μA
μA
μA
μA
V
(maximum)
High sustaining VIN < VIH
–25
–30
–50
–70
current
(minimum)
Low overdrive
current
0 V < VIN
VCCIO
<
160
–160
1.0
200
–200
1.07
300
–300
1.7
500
–500
2.0
High overdrive 0 V < VIN
<
current
VCCIO
Bus-hold trip
point
0.5
0.68
0.7
0.8
Notes to Tables 6–14 through 6–33:
(1) Drive strength is programmable according to values in the Stratix GX Architecture chapter of the Stratix GX Device
Handbook, Volume 1.
(2) VREF specifies the center point of the switching range.
Detailed power consumption information for Stratix GX devices will be
released when available.
Power
Consumption
The DirectDrive™ technology and MultiTrack™ interconnect ensure
Timing Model
predictable performance, accurate simulation, and accurate timing
analysis across all Stratix GX device densities and speed grades. This
section describes and specifies the performance, internal, external, and
PLL timing specifications.
All specifications are representative of worst-case supply voltage and
junction temperature conditions.
Preliminary & Final Timing
Timing models can have either preliminary or final status. The
Quartus® II software displays an informational message during the
design compilation if the timing models are preliminary. Table 6–34
shows the status of the Stratix GX device timing models.
6–22
Altera Corporation
August 2005
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
