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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
2.5-V, or 3.3-V power supply, depending on the output requirements.  
The output levels are compatible with systems of the same voltage as the  
power supply (for example, when VCCIOpins are connected to a 1.5-V  
power supply, the output levels are compatible with 1.5-V systems).  
When VCCIOpins are connected to a 3.3-V power supply, the output high  
is 3.3 V and is compatible with 3.3-V or 5.0-V systems.  
Table 4–32 summarizes Stratix GX MultiVolt I/O support.  
Table 4–32. Stratix GX MultiVolt I/O Support  
Input Signal (5)  
1.5 V 1.8 V 2.5 V 3.3 V 5.0 V 1.5 V 1.8 V 2.5 V 3.3 V 5.0 V  
Note (1)  
Output Signal (6)  
VCCIO (V)  
1.5  
1.8  
2.5  
3.3  
v
v (2)  
v
v
v
v (3)  
v (3) v (3)  
v (2) v (2)  
v (2) v (2)  
v
v
v
v
v
v
v
v (2)  
v (4) v (3) v (3) v (3)  
Notes to Table 4–32:  
(1) To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V  
inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V.  
(2) The input pin current may be slightly higher than the typical value.  
(3) Although VCCIO specifies the voltage necessary for the Stratix GX device to drive out, a receiving device powered  
at a different level can still interface with the Stratix GX device if it has inputs that tolerate the VCCIO value.  
(4) Stratix GX devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.  
(5) This is the external signal that is driving the Stratix GX device.  
(6) This represents the system voltage that Stratix GX supports when a VCCIO pin is connected to a specific voltage  
level. For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal  
coming out from Stratix GX is 3.3 V and is compatible with 3.3-V or 5.0-V systems.  
Because Stratix GX devices can be used in a mixed-voltage environment,  
they have been designed specifically to tolerate any possible power-up  
sequence. Therefore, the VCCIOand VCCINTpower supplies may be  
powered in any order.  
Power  
Sequencing &  
Hot Socketing  
Signals can be driven into Stratix GX devices before and during power up  
without damaging the device. In addition, Stratix GX devices do not  
drive out during power up. Once operating conditions are reached and  
the device is configured, Stratix GX devices operate as specified by the  
user. For more information, see the Selectable I/O Standards in Stratix &  
Stratix GX Devices chapter of the Stratix GX Device Handbook, Volume 2.  
Altera Corporation  
February 2005  
4–121  
Stratix GX Device Handbook, Volume 1  
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