Stratix GX Architecture
Table 4–28 shows I/O standard support for each I/O bank.
Table 4–28. I/O Support by Bank (Part 1 of 2)
Top & Bottom Banks
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
Left Banks
(1 & 2)
I/O Standard
(3, 4, 7 & 8)
LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
v
v
v
v
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL (clock
inputs)
v
v
Differential HSTL (clock
outputs)
v
v
Differential SSTL (clock
outputs)
3.3-V GTL
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V GTL+
v
v
1.5-V HSTL class I
1.5-V HSTL class II
1.8-V HSTL class I
1.8-V HSTL class II
SSTL-18 class I
SSTL-18 class II
SSTL-2 class I
SSTL-2 class II
SSTL-3 class I
v
v
v
v
v
Altera Corporation
February 2005
4–117
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
