TriMatrix Memory
Figure 4–25. Input/Output Clock Mode in Simple Dual-Port Mode
Note (1)
8 LAB Row
Clocks
Memory Block
8
256 ´ 16
512 ´ 8
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
data[ ]
address[ ]
byteena[ ]
D
ENA
Q
Q
Q
Data In
Read Address
D
ENA
To MultiTrack
Interconnect
Data Out
D
Q
ENA
Byte Enable
D
ENA
wraddress[ ]
rden
Write Address
Read Enable
D
ENA
Q
Q
D
ENA
wren
outclken
Write
Pulse
Generator
D
ENA
Q
Write Enable
inclken
wrclock
rdclock
Note to Figure 4–25:
(1) All registers shown except the rdenregister have asynchronous clear ports.
Read/Write Clock Mode
The memory blocks implement read/write clock mode for simple dual-
port memory. You can use up to two clocks in this mode. The write clock
controls the block’s data inputs, wraddress, and wren. The read clock
controls the data output, rdaddress, and rden. The memory blocks
support independent clock enables for each clock and asynchronous clear
signals for the read- and write-side registers. Figure 4–26 shows a
memory block in read/write clock mode.
4–44
Stratix GX Device Handbook, Volume 1
Altera Corporation
February 2005
ALTERA [ ALTERA CORPORATION ]
