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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix GX Architecture  
the capabilities for dynamic and mixed sign multiplications are handled  
differently. The following list provides the largest functions that can fit  
into a single DSP block.  
36 × 36-bit unsigned by unsigned multiplication  
36 × 36-bit signed by signed multiplication  
35 × 36-bit unsigned by signed multiplication  
36 × 35-bit signed by unsigned multiplication  
36 × 35-bit signed by dynamic sign multiplication  
35 × 36-bit dynamic sign by signed multiplication  
35 × 36-bit unsigned by dynamic sign multiplication  
36 × 35-bit dynamic sign by unsigned multiplication  
35 × 35-bit dynamic sign multiplication when the sign controls for  
each operand are different  
36 × 36-bit dynamic sign multiplication when the same sign control  
is used for both operands  
1
This list only shows functions that can fit into a single DSP block.  
Multiple DSP blocks can support larger multiplication  
functions.  
Figure 4–28 shows one of the columns with surrounding LAB rows.  
Altera Corporation  
February 2005  
4–47  
Stratix GX Device Handbook, Volume 1  
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