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EP1SGX40GF1020I6N 参数 Datasheet PDF下载

EP1SGX40GF1020I6N图片预览
型号: EP1SGX40GF1020I6N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 4697 CLBs, 41250-Cell, CMOS, PBGA1020, 33 X 33 MM, 1 MM PITCH, LEAD FREE, FBGA-1020]
分类和应用: 可编程逻辑
文件页数/大小: 279 页 / 3682 K
品牌: ALTERA [ ALTERA CORPORATION ]
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TriMatrix Memory  
Independent Clock Mode  
The memory blocks implement independent clock mode for true dual-  
port memory. In this mode, a separate clock is available for each port  
(ports A and B). Clock A controls all registers on the port A side, while  
clock B controls all registers on the port B side. Each port, A and B, also  
supports independent clock enables and asynchronous clear signals for  
port A and B registers. Figure 4–23 shows a TriMatrix memory block in  
independent clock mode.  
4–40  
Stratix GX Device Handbook, Volume 1  
Altera Corporation  
February 2005  
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