Stratix GX Architecture
Figure 4–26. Read/Write Clock Mode in Simple Dual-Port Mode
Note (1)
8 LAB Row
Clocks
Memory Block
256 × 16
512 × 8
8
1,024 × 4
data[ ]
D
ENA
Q
Data In
2,048 × 2
4,096 × 1
To MultiTrack
Interconnect
Data Out
D
Q
ENA
address[ ]
Read Address
D
Q
Q
Q
ENA
wraddress[ ]
Write Address
Byte Enable
Read Enable
D
ENA
byteena[ ]
rden
D
ENA
D
Q
ENA
wren
outclken
Write
Pulse
Generator
D
ENA
Q
inclken
wrclock
Write Enable
rdclock
Note to Figure 4–26:
(1) All registers shown except the rdenregister have asynchronous clear ports.
Single-Port Mode
The memory blocks also support single-port mode, used when
simultaneous reads and writes are not required. See Figure 4–27. A single
block in a memory block can support up to two single-port mode RAM
blocks in the M4K RAM blocks if each RAM block is less than or equal to
2K bits in size.
Altera Corporation
February 2005
4–45
Stratix GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
