DC & Switching Characteristics
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 2
of 2) Notes (1), (2)
Symbol
Parameter
tXZPLL
Synchronous IOE output enable register to output pin disable delay
using regional clock fed by Enhanced PLL with default phase setting
tZXPLL
Synchronous IOE output enable register to output pin enable delay
using regional clock fed by Enhanced PLL with default phase setting
Notes to Table 4–53:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Table 4–54 shows the external I/O timing parameters when using global
clock networks.
Table 4–54. Stratix Global Clock External I/O Timing Parameters Notes (1),
(2)
Symbol
Parameter
tINSU
Setup time for input or bidirectional pin using IOE input register with
global clock fed by CLKpin
tINH
Hold time for input or bidirectional pin using IOE input register with
global clock fed by CLKpin
tOUTCO
tINSUPLL
tINHPLL
Clock-to-output delay output or bidirectional pin using IOE output
register with global clock fed by CLKpin
Setup time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
global clock fed by Enhanced PLL with default phase setting
tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output
register with global clock Enhanced PLL with default phase setting
tXZPLL
Synchronous IOE output enable register to output pin disable delay
using global clock fed by Enhanced PLL with default phase setting
tZXPLL
Synchronous IOE output enable register to output pin enable delay
using global clock fed by Enhanced PLL with default phase setting
Notes to Table 4–54:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Altera Corporation
July 2005
4–35
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
