DC & Switching Characteristics
External Timing Parameters
External timing parameters are specified by device density and speed
grade. Figure 4–4 shows the pin-to-pin timing model for bidirectional
IOE pin timing. All registers are within the IOE.
Figure 4–4. External Timing in Stratix Devices
OE Register
PRN
D
Q
t
t
t
t
t
INSU
INH
OUTCO
XZ
Dedicated
Clock
CLRN
ZX
Output Register
PRN
Bidirectional
Pin
D
Q
CLRN
Input Register
PRN
D
Q
CLRN
All external timing parameters reported in this section are defined with
respect to the dedicated clock pin as the starting point. All external I/O
timing parameters shown are for 3.3-V LVTTL I/O standard with the
24-mA current strength and fast slew rate. For external I/O timing using
standards other than LVTTL or for different current strengths, use the I/O
standard input and output delay adders in Tables 4–103 through 4–108.
Altera Corporation
July 2005
4–33
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
