Timing Model
Stratix External I/O Timing
These timing parameters are for both column IOE and row IOE pins. In
EP1S30 devices and above, you can decrease the tSU time by using the
FPLLCLK, but may get positive hold time in EP1S60 and EP1S80 devices.
You should use the Quartus II software to verify the external devices for
any pin.
Tables 4–55 through 4–60 show the external timing parameters on column
and row pins for EP1S10 devices.
Table 4–55. EP1S10 External I/O Timing on Column Pins Using Fast Regional Clock Networks Note (1)
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
Min
Max
tINSU
2.238
0.000
2.240
2.180
2.180
2.325
0.000
2.240
2.180
2.180
2.668
0.000
2.240
2.180
2.180
NA
NA
NA
NA
NA
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
4.549
4.423
4.423
4.836
4.704
4.704
5.218
5.094
5.094
NA
NA
NA
tZX
Table 4–56. EP1S10 External I/O Timing on Column Pins Using Regional Clock Networks Note (1)
-5 Speed Grade
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Parameter
Unit
Min
Max
Min
Max
Min
Max
tINSU
1.992
0.000
2.395
2.335
2.335
0.975
0.000
1.262
1.202
1.202
2.054
0.000
2.395
2.335
2.335
0.985
0.000
1.262
1.202
1.202
2.359
0.000
2.395
2.335
2.335
1.097
0.000
1.262
1.202
1.202
NA
NA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tINH
tOUTCO
tXZ
4.795
4.669
4.669
5.107
4.975
4.975
5.527
5.403
5.403
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
tZX
tINSUPLL
tINHPLL
tOUTCOPLL
tXZPLL
tZXPLL
NA
NA
NA
NA
2.636
2.510
2.510
2.680
2.548
2.548
2.769
2.645
2.645
4–36
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
