欢迎访问ic37.com |
会员登录 免费注册
发布采购

EP1S80B1508C7ES 参数 Datasheet PDF下载

EP1S80B1508C7ES图片预览
型号: EP1S80B1508C7ES
PDF下载: 下载PDF文件 查看货源
内容描述: Stratix器件系列数据手册 [Stratix Device Family Data Sheet]
分类和应用:
文件页数/大小: 290 页 / 3583 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号EP1S80B1508C7ES的Datasheet PDF文件第210页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第211页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第212页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第213页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第215页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第216页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第217页浏览型号EP1S80B1508C7ES的Datasheet PDF文件第218页  
Timing Model  
Table 4–52 shows the external I/O timing parameters when using fast  
regional clock networks.  
Table 4–52. Stratix Fast Regional Clock External I/O Timing Parameters  
Notes (1), (2)  
Symbol  
Parameter  
tINSU  
Setup time for input or bidirectional pin using IOE input register with  
fast regional clock fed by FCLKpin  
tINH  
Hold time for input or bidirectional pin using IOE input register with  
fast regional clock fed by FCLKpin  
tOUTCO  
tXZ  
Clock-to-output delay output or bidirectional pin using IOE output  
register with fast regional clock fed by FCLKpin  
Synchronous IOE output enable register to output pin disable delay  
using fast regional clock fed by FCLKpin  
tZX  
Synchronous IOE output enable register to output pin enable delay  
using fast regional clock fed by FCLKpin  
Notes to Table 4–52:  
(1) These timing parameters are sample-tested only.  
(2) These timing parameters are for column and row IOE pins. You should use the  
Quartus II software to verify the external timing for any pin.  
Table 4–53 shows the external I/O timing parameters when using  
regional clock networks.  
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 1  
of 2) Notes (1), (2)  
Symbol  
Parameter  
tINSU  
Setup time for input or bidirectional pin using IOE input register with  
regional clock fed by CLKpin  
tINH  
Hold time for input or bidirectional pin using IOE input register with  
regional clock fed by CLKpin  
tOUTCO  
tINSUPLL  
tINHPLL  
Clock-to-output delay output or bidirectional pin using IOE output  
register with regional clock fed by CLKpin  
Setup time for input or bidirectional pin using IOE input register with  
regional clock fed by Enhanced PLL with default phase setting  
Hold time for input or bidirectional pin using IOE input register with  
regional clock fed by Enhanced PLL with default phase setting  
tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output  
register with regional clock Enhanced PLL with default phase setting  
4–34  
Stratix Device Handbook, Volume 1  
Altera Corporation  
July 2005  
 复制成功!