Timing Model
Table 4–52 shows the external I/O timing parameters when using fast
regional clock networks.
Table 4–52. Stratix Fast Regional Clock External I/O Timing Parameters
Notes (1), (2)
Symbol
Parameter
tINSU
Setup time for input or bidirectional pin using IOE input register with
fast regional clock fed by FCLKpin
tINH
Hold time for input or bidirectional pin using IOE input register with
fast regional clock fed by FCLKpin
tOUTCO
tXZ
Clock-to-output delay output or bidirectional pin using IOE output
register with fast regional clock fed by FCLKpin
Synchronous IOE output enable register to output pin disable delay
using fast regional clock fed by FCLKpin
tZX
Synchronous IOE output enable register to output pin enable delay
using fast regional clock fed by FCLKpin
Notes to Table 4–52:
(1) These timing parameters are sample-tested only.
(2) These timing parameters are for column and row IOE pins. You should use the
Quartus II software to verify the external timing for any pin.
Table 4–53 shows the external I/O timing parameters when using
regional clock networks.
Table 4–53. Stratix Regional Clock External I/O Timing Parameters (Part 1
of 2) Notes (1), (2)
Symbol
Parameter
tINSU
Setup time for input or bidirectional pin using IOE input register with
regional clock fed by CLKpin
tINH
Hold time for input or bidirectional pin using IOE input register with
regional clock fed by CLKpin
tOUTCO
tINSUPLL
tINHPLL
Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock fed by CLKpin
Setup time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
Hold time for input or bidirectional pin using IOE input register with
regional clock fed by Enhanced PLL with default phase setting
tOUTCOPLL Clock-to-output delay output or bidirectional pin using IOE output
register with regional clock Enhanced PLL with default phase setting
4–34
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005