Stratix Architecture
Figure 2–42. Global Clocking Note (1)
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
CLK[11..8]
Global Clock [15..0]
CLK[7..4]
Note to Figure 2–42:
(1) The corner fast PLLs can also be driven through the global or regional clock
networks. The global or regional clock input to the fast PLL can be driven by an
output from another PLL, a pin-driven global or regional clock, or internally-
generated global signals.
Regional Clock Network
There are four regional clock networks within each quadrant of the Stratix
device that are driven by the same dedicated CLK[15..0]input pins or
from PLL outputs. From a top view of the silicon, RCLK[0..3]are in the
top left quadrant, RCLK[8..11]are in the top-right quadrant,
RCLK[4..7]are in the bottom-left quadrant, and RCLK[12..15]are in
the bottom-right quadrant. The regional clock networks only pertain to
the quadrant they drive into. The regional clock networks provide the
lowest clock delay and skew for logic contained within a single quadrant.
RCLKcannot be driven by internal logic. The CLKclock pins
symmetrically drive the RCLKnetworks within a particular quadrant, as
shown in Figure 2–43. See Figures 2–50 and 2–51 for RCLKconnections
from PLLs and CLKpins.
Altera Corporation
July 2005
2–75
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
