Stratix Architecture
Figure 2–46. Regional Clock Bus
Clocks Available
to a Quadrant
or Half-Quadrant
Vertical I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Regional Clock Network [3..0]
Clock [21..0]
Lab Row Clock [7..0]
Fast Regional Clock Network [1..0]
Horizontal I/O
Cell IO_CLK[7..0]
IOE clocks have horizontal and vertical block regions that are clocked by
eight I/O clock signals chosen from the 22 quadrant or half-quadrant
clock resources. Figures 2–47 and 2–48 show the quadrant and half-
quadrant relationship to the I/O clock regions, respectively. The vertical
regions (column pins) have less clock delay than the horizontal regions
(row pins).
Altera Corporation
July 2005
2–79
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
