PLLs & Clock Networks
Figure 2–43. Regional Clocks
RCLK[2..3]
RCLK[11..10]
CLK[15..12]
RCLK[1..0]
CLK[3..0]
RCLK[9..8]
CLK[11..8]
RCLK[4..5]
RCLK[14..15]
CLK[7..4]
Regional Clocks Only Drive a Device
Quadrant from Specified CLK Pins or
PLLs within that Quadrant
RCLK[6..7] RCLK[12..13]
Fast Regional Clock Network
In EP1S25, EP1S20, and EP1S10 devices, there are two fast regional clock
networks, FCLK[1..0], within each quadrant, fed by input pins that can
connect to fast regional clock networks (see Figure 2–44). In EP1S30 and
larger devices, there are two fast regional clock networks within each
half-quadrant (see Figure 2–45). Dual-purpose FCLKpins drive the fast
clock networks. All devices have eight FCLKpins to drive fast regional
clock networks. Any I/O pin can drive a clock or control signal onto any
fast regional clock network with the addition of a delay. This signal is
driven via the I/O interconnect. The fast regional clock networks can also
be driven from internal logic elements.
2–76
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
