PLLs & Clock Networks
Figure 2–45. EP1S30 Device Fast Regional Clock Pin Connections to Fast
Regional Clocks
FCLK1
FCLK0
FCLK7
FCLK6
(1), (2)
(1), (2)
(1), (2)
(1), (2)
fclk[1..0]
(1), (2)
(1), (2)
(1), (2)
(1), (2)
FCLK3
FCLK2
FCLK5
FCLK4
Notes to Figure 2–45:
(1) This is a set of two multiplexers.
(2) In addition to the FCLKpin inputs, there is also an input from the I/O interconnect.
Combined Resources
Within each region, there are 22 distinct dedicated clocking resources
consisting of 16 global clock lines, four regional clock lines, and two fast
regional clock lines. Multiplexers are used with these clocks to form eight
bit busses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select two of the eight row
clocks to feed the LE registers within the LAB. See Figure 2–46.
2–78
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
